The present invention relates generally to an electronic package for one or more integrated circuits and to a method for designing the package. An integrated circuit includes a large number of circuit elements such as transistors formed in a semiconductor substrate and an interconnection array defined in alternating layers of an insulating material and a conducting material formed on top of the circuit elements. Illustratively, in state of the art integrated circuits, interconnection paths may be defined in twelve or more layers of conducting material to provide signal, power and ground connections to the circuit elements. The side of the semiconductor substrate with the circuit elements and interconnection array is often referred to as the front side or the active side. The opposite side of the substrate is referred to as the back side.
It frequently is desirable to mount an integrated circuit on another surface. To ensure good contact between the integrated circuit and the other surface, it is critical that the two joining surfaces be substantially parallel at the joining temperature. Illustratively, the surfaces are joined by two dimensional arrays of solder balls or solder bumps that are typically copper.
Warpage of the integrated circuit that causes non-parallel bonding surfaces is a constant concern in semiconductor fabrication. One example of a warpage problem is that caused by use of thick metal layers in power distribution networks in the interconnection array on an integrated circuit. In this example which is summarized in Table I below, several integrated circuit wafers are fabricated at a 20 nanometer (nm.) technology node using twelve metal layers, the uppermost of which is approximately three times the thickness of most of the underlying layers. The wafers are identified in column A. The warpage in microns of the wafers before formation of the uppermost metallization layer is set forth in column B and the warpage of the wafers after formation of the uppermost layer is set forth in column C. As can be seen, the uppermost layer changes the warpage of each wafer from a positive warpage of approximately 30 microns (μ) where a positive warpage indicates a concave shape on the front side of the substrate to a negative warpage of approximately 150 where a negative warpage indicates a convex shape. These large negative numbers are not acceptable.
TABLE ICOLUMN ACOLUMN BCOLUMN C127.3−177.1235.9−157.2332.8−140.4434.3−149.9535.4−143.5637.7−137.6
As a general rule, warpage tends to increase with increasing die size. As a result, a stack of metal layers used on a small die may not produce excessive warpage while the same stack of metal layers used on a larger die may produce excessive warpage.